Politecnico di Torino - Corso Duca degli Abruzzi, 24 - 10129 Torino, ITALY

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automatic codingCode complexity metricsInformatica Tsd Enparallel codingproductivity


Process for the automatic generation of parallel calculation code with a high level of abstraction which can be performed on electronic processors with multi-core, many-core or heterogeneous hybrid architectures.

Technical features

The aim of the present invention is to solve the difficulties related to multi-architecture parallel programming. It uses an innovative and automatic process for the generation of high-performance parallel code executable on multi-core and many-core computing systems. This code is generated automatically starting from code developed according to the structures typically used for sequential coding. The use of this procedure considerably reduces objective metrics generally adopted for measuring the complexity of programs and the effort to write them. Finally, this procedure allows the optimisation of the generated parallel code depending on the target architecture, without altering the source but intervening on parameters that are independent of the application code.

Possible Applications

  • Computer vision;
  • Autonomous driving;
  • Big-data processing;
  • Robotics;
  • Modeling of physical phenomena (e.g. mechanical models, meteorology);
  • Physics;
  • Games;
  • Advanced graphics;
  • Multimedia content processing;
  • App.


  • Facilitation of the programmer’s task by autonomously generating the parallel code;
  • Considerable reduction of the objective metrics generally adopted to measure the complexity of the programs and the effort to write them, such as “lines of code” (LOC), “Halstead’s mental discrimination” [HMD] and “McCabe’s total cyclomatic complexity” [TCYC];
  • Easy to apply even on machines with different architectures;
  • Decoupling of application semantics from high-performance parallel code encoding that is performed by a multi-core (CPU) or many-core (GPU) architecture;
  • Complete decoupling between the regulation of these parallelization parameters and the actual expression of the computation;
  • Not alteration of the code written by the programmer.