Introduction

A computing platform and method to synchronize the prototype execution and simulation of hardware devices.

Technical features

Using a general purpose CPU that carries out the application, the System on Chip is enhanced by a physical pin and the associated hardware infrastructure that implements the command semantics of that pin. The infrastructure makes it possible for time windows to be created during the execution of the application on the prototype by moving the physical pin between logical states “1” and “0”. As with breakpoints, the user can set addresses that correspond to the program instructions for creating the observation window. This window is accurate in terms of the clock cycle, and requires no additional user code. The same infrastructure can be used in simulation to synchronize with execution on the prototype in order to perform different analyses on the design. Note that we have a working prototype that implements the proposal. Moreover, this infrastructure has also been implemented for hardware accelerators, i.e., digital systems for which the computation unit does not execute software code but implements a predefined algorithm that processes the data in input (the hardware accelerators).

Possible Applications

• Execution on the prototype (black-box);
• Micron, Infineon, Intel, AMD, ARM and anyone interested in making the chip could be interested;
• FPGA (Xilinx, Altera/Intel) or ASIC (Cadence, Synopsis);
• Debugging hardware.

Advantages

• It isn’t a mechanism for debugging software;
• It doesn’t require an additional user code (which could reduce the quality of the resolution of the time quality);
• It could considerably to the traditional techniques of circuit analysis.