Introduction

The invention consists of a method to automatically instrument digital hardware calculation circuits, so that their precision and power consumption can be configured at runtime, with a low reconfiguration time and with limited area and power overheads at maximum precision. Such circuits can be applied to all so-called “error resilient” applications, such as multimedia, radio and machine learning.

Technical features

A standard-cell-based digital calculation circuit is automatically split into multiple fine-grain power domains. Depending on the required precision and on the target clock frequency, the operating conditions of the power domains are altered to allow timing compliance with minimum total power consumption. Power domains can be either identical squares, constructed following a grid, or irregular rectangles, constructed based on an analysis of the relevance of each standard cell’s switching delay at various precisions. The former solution has better regularity properties whereas the latter achieves higher energy efficiency. The runtime knobs used to affect the speed and power of the fine-grain domains are the supply voltage and threshold voltage of the transistors. Therefore, the invention is particularly effective for IC technologies in which threshold voltage scaling has a strong impact on speed and power, such as FDSOI.

Possible Applications

• Multimedia (audio and video) processing hardware design;
• Radio Signals processing hardware design;
• Machine learning hardware design;
• Deep learning hardware design;
• Hardware design for all other “error resilient” applications.

Advantages

• Automatic instrumentation flow;
• Compatible with industrial software for digital IC design;
• Applicable to all main calculation circuits;
• Short reconfiguration time;
• Low area and power overheads at maximum precision.